1. Field of the Invention
The present invention relates to a method of forming a gate of a flash memory cell, by which a coupling effect between floating and control gates can be enhanced by forming a polysilicon spacer to increase a surface area of the floating gate.
2. Discussion of the Related Art
Generally, a non-volatile semiconductor device enables to store data therein without power supply provided thereto as well as enables electrical data erase and write, and its application range expands in various fields.
The non-volatile semiconductor devices are categorized into the NAND type for high degree of device integration and the NOR type for high speed according to memory cell array structures thereof, respectively. Hence, their advantages are utilized popular for many applications.
The NOR type non-volatile semiconductor device directly associated with the present invention consists of a plurality of memory cells, each of which comprises a single transistor, connected parallel to one bit line. Specifically, one cell transistor is connected between a drain connected to the bit line and a source connected to a common source line to enable current increase and high-speed operation of the memory cell. Yet, areas occupied by a bit line contact and source line are increased to have difficulty in achieving high memory device integration.
In the above-featured NO type non-volatile semiconductor device, a memory cell is configured in a manner of stacking a floating gate, insulating interlayer, and control gate in turn. And, a series of device operations associated with data storage, erase, and read are performed in a following manner. In doing so, a programming associated with the data storage is performed by hot electron injection or F-N (fowler-Nordheim) tunneling and an erasing associated with the data erase is performed by F-N tunneling. In the following example, the programming is performed by hot electron injection.
First of all, the programming is explained. By applying a voltage to the bit line and the control gate to form a channel between the source and drain, hot electrons are generated from the drain. The generated electrons go over a gate insulating layer barrier or a tunneling insulating layer barrier due to the gate voltage to be injected into the floating gate. Hence, the programming is achieved so that data can be written in an erased cell.
Thus, if the floating gate is filled with electrons, a threshold voltage of the memory cell is raised by the electrons. If the cell is read by supplying a power source voltage (3.3V or 5V) to the control gate connected to the wordline, a current fails to flow therein since a channel fails to be formed due to the high threshold voltage. Hence, one kind of state can be memorized.
Meanwhile, in case of performing the erasing to store new information, the control gate is grounded and a strong electric field is applied between both ends of the gate insulating layer between the floating gate and the substrate by applying high voltage to the source. If so, the gate insulating layer barrier becomes thinner so that the electrons stored within the floating gate by F-N tunneling penetrate the thin insulating layer barrier to drain toward the substrate. Hence, the data erase is completed. As a result, there exist no electrons in the floating gate to lower the threshold voltage of the cell. If the cell is read by applying the power source voltage to the control gate, one state different from the previous state can be memorized.
Namely, the data read is performed in a manner of deciding a presence or non-presence of current of the memory cell transistor by applying an appropriate voltage to the bit line and control gate of the selected cell.
FIG. 1A and FIG. 1B are cross-sectional diagrams for explaining a method of forming a gate according to a related art.
FIG. 1A shows a step of depositing a gate insulating layer, a first conductor layer, a first insulating layer, and a second insulating layer.
Referring to FIG. 1A, a gate insulating layer 11 is formed on a substrate 10 having a prescribed device formed therein. A first conductor layer 12 for forming a floating gate is deposited on the gate insulating layer 11. And, a first insulating layer 13 and a second insulating layer 14 are stacked on the first conductor layer 12 for insulation between a control gate and floating gate that will be formed later. In doing so, the gate insulating layer 11 may be formed of either oxide or nitride. Preferably, the gate insulating layer 11 is formed of an upper oxide layer/nitride layer/lower oxide layer to have an ONO (oxide-nitride-oxide) structure.
Moreover, the first conductor layer 12 is formed in a manner of depositing silicon and crystallizing the deposited silicon into polysilicon or mono-crystalline silicon, which will be etched to form the floating gate. Preferably, the first and second insulating layers 13 and 14 are formed of oxide and nitride, respectively.
FIG. 1B shows a step of etching the second insulating layer, the first insulating layer, and the first conductor layer in turn to form a gate.
Referring to FIG. 1B, photoresist is coated on the second insulating layer. And, exposure and development are carried out on the photoresist to form a photoresist pattern (not shown in the drawing).
Subsequently, the second insulating layer, the first insulating layer, and the first conductor layer are etched using the photoresist pattern to form a floating gate pattern including the floating gate 15. In doing so, the oxide layer of the gate insulating layer 11 can be used as an etch stop layer.
However, in the related art gate forming method, a junction area between the control and floating gates is limited to a surface area of the floating gate only, whereby a coupling effect is small.